1. Field of the Invention
The present invention relates to a display panel control circuit for controlling the operation of a display panel, such as a liquid crystal panel, or the like, and specifically to a display panel control circuit for simultaneously driving two display panels which operate based on different driving methods.
2. Description of the Prior Art
The liquid crystal display device which displays images using so-called liquid crystals has been widespread. For example, the liquid crystal display device, which includes a control circuit of a liquid crystal panel, is incorporated in a digital video camera (DVC), a digital still camera (DSC), or other AV devices.
A conventional liquid crystal panel control circuit is now described with reference to FIGS. 4 to 10. FIG. 4 is a block circuit diagram showing a structure of the conventional liquid crystal panel control circuit. FIG. 5 is a block circuit diagram showing a detailed structure of the conventional liquid crystal panel control circuit. This control circuit is used for a digital video camera having two liquid crystal panels, or the like.
The conventional display panel control circuit includes a voltage controlled oscillator (VCO) 1100, a horizontal system driving pulse generation section 1700 which works for first and second panels, a phase comparator 1300 for outputting a phase error between horizontal synchronization signal HD input through a horizontal synchronization signal input terminal 1010 and a phase-compared signal which is an output signal of the horizontal system driving pulse generation section 1700, a smoothing element (LPF) 1400 for smoothing the phase error output from the phase comparator 1300 and feeding back the smoothed phase error to the VCO 1100, and a vertical system driving pulse generation section 1600 for the first and second panels, which receives signal VCLK output from the horizontal system driving pulse generation section 1700 and vertical synchronization signal VD input through a vertical synchronization signal input terminal 1020. In the conventional display panel control circuit, the operations of the VCO 1100, the horizontal system driving pulse generation section 1700 and the vertical system driving pulse generation section 1600 are switched according to panel selection signal SEL. Specifically, the signal input to the horizontal system driving pulse generation section 1700 is switched between a signal for the first panel and a signal for the second panel according to the “High”/“Low” of panel selection signal SEL. More specifically, the VCO 1100 outputs clock signal VCOCLK1 for the first panel or clock signal VCOCLK2 for the second panel according to panel selection signal SEL. The horizontal system driving pulse generation section 1700 outputs a group of horizontal system outputs for the first panel through a horizontal system output group terminal 1030 for the first panel or a group of horizontal system outputs for the second panel through a horizontal system output group terminal 1050 for the second panel according to panel selection signal SEL. The vertical system driving pulse generation section 1600 outputs a group of vertical system outputs for the first panel through a first-panel vertical system output group terminal 1040 or a group of vertical system outputs for the second panel through a second-panel vertical system output group terminal 1060 according to panel selection signal SEL.
The liquid crystal panel driving methods include a single-pixel sequential transfer method wherein three pixels corresponding to R (red), G (green) and B (blue) are sequentially driven and a three-pixel simultaneous transfer method wherein three pixels of R, G and B are simultaneously driven for display. In the single-pixel sequential transfer method, the horizontal shift clock is mainly realized by pulse signals of three phases. In three-pixel simultaneous transfer method, the horizontal shift clock is mainly realized by pulse signals of two phases.
In a liquid crystal panel wherein pixels are in a delta arrangement, it is necessary to control the phase of the horizontal shift clock such that the phase conforms to the pixel arrangement in each of the odd-numbered row (ODD line) and the even-numbered row (EVEN line).
FIG. 5 shows an example of a display panel control circuit for controlling a panel based on the single-pixel sequential transfer method (first panel) and a panel based on the three-pixel simultaneous transfer method (second panel).
In the horizontal system driving pulse generation section 1700 of the display panel control circuit of FIG. 5, signal VCOCLK1 or VCOCLK2 output from the VCO 1100 is input to a ⅙ frequency divider 1210, and signal HCLK1 output from the ⅙ frequency divider 1210 is used as a clock signal in an H-counter (1) 1220. Signal HCLK1 is also input to a first-panel horizontal shift clock generation section 1230 and a second-panel horizontal shift clock generation section 1530.
One of the plurality of signals output from the H-counter (1) 1220 is supplied to the phase comparator 1300. Output signal VCLK is supplied to the vertical system driving pulse generation section 1600. A group of the other signals output from the H-counter (1) 1220 is transmitted to the horizontal system output group terminal 1030 or the horizontal system output group terminal 1050.
The first-panel horizontal shift clock generation section 1230 includes a ½ frequency divider 1231 which receives HCLK1 as a clock, a shift register 1232 which receives VCOCLK1 or VCOCLK2 output from the VCO 1100 as a clock, a switch section 1233 for switching the phase of the signal output from the shift register 1232 between the ODD lines and the EVEN lines of a liquid crystal panel where pixels are in a delta arrangement. The first-panel horizontal shift clock generation section 1230 outputs horizontal shift clocks CPH1, CPH2 and CPH3 of three different phases for the first panel, which are the output signals of the switch section 1233, through a first-panel horizontal shift clock output terminal 1035.
The second-panel horizontal shift clock generation section 1530 includes an inverter 1534 which receives HCLK1, a D-type flip flop (D-FF) 1532 which receives the output of the inverter 1534 as a clock and the output of the ½ frequency divider 1231 as a D-input, and a switch section 1533 for switching the output of the ½ frequency divider 1231 and the output of the D-FF 1532 between the ODD lines and the EVEN lines of a liquid crystal panel where pixels are in a delta arrangement. The switch section 1533 outputs horizontal shift clocks CKH1 and CKH2 of two different phases for the second panel through a second-panel horizontal shift clock output terminal 1055.
The vertical system driving pulse generation section 1600 includes a V-counter (1) 1610 which receives signal VCLK as a clock input and an inversion section 1640 for inverting the logic of each output of the V-counter (1) 1610. A group of the outputs of the inversion section 1640 is output to the first-panel vertical system output group terminal 1040 or the second-panel vertical system output group terminal 1060.
In the conventional display panel control circuit described herein, the operations of the VCO 1100, the horizontal system driving pulse generation section 1700 and the vertical system driving pulse generation section 1600 are switched according to panel selection signal SEL between the operations for the first panel and the operations for the second panel.
FIG. 6 is a circuit diagram showing a structure of a part of the conventional display panel control circuit. FIG. 6 shows the connections of the ½ frequency divider 1231 which is a component of the first-panel horizontal shift clock generation section 1230 and the D-FF 1532 and the inverter 1534 which are components of the second-panel horizontal shift clock generation section 1530. In FIG. 6, “CKHO” is the output signal of the ½ frequency divider 1231, and “CKHE” is the output signal of the D-FF 1532. The waveforms of these signals are shown in FIG. 8.
FIG. 8 shows the waveforms of the horizontal shift clocks for the first and second panels which are output from the conventional display panel control circuit. Herein, output signal CKHO of the ½ frequency divider 1231 is a horizontal shift clock for the ODD lines of the second panel, and output signal CKHE of the D-FF 1532 is a horizontal shift clock for the EVEN lines of the second panel. It should be noted that the ODD line horizontal shift clock and the EVEN line horizontal shift clock may be replaced by each other. As shown in FIG. 8, signal HCLK1 is obtained by dividing the frequency of VCOCLK1 or VCOCLK2 by 6, signal CKHO is obtained by dividing the frequency of HCLK1 by 2, and the phase of signal CKHE is different from that of signal CKHO by 90°.
FIG. 7 is a circuit diagram showing an example of a detailed structure of the shift register 1232 which is a component of the first-panel horizontal shift clock generation section 1230. In the shift register 1232, signal CKHO output from the ½ frequency divider 1231 is delayed using signal VCOCLK1 or VCOCLK2 output from the VCO 1100 on a 2-clock by 2-clock basis, and resultant signals are input to EX-OR and EX-NOR gates, thereby obtaining output signals CPH1, CPH2 and CPH3 of three different phases where a period corresponding to two clock cycles of signal VCOCLK1 or VCOCLK2 is High period. Signals CPH1, CPH2 and CPH3 of FIG. 8 are the horizontal shift clocks for the ODD lines of the first panel. Signals obtained by delaying signals CPH1, CPH2 and CPH3 by one clock cycle of VCOCLK1 or VCOCLK2 are used as the horizontal shift clocks for the EVEN lines. The circuit for obtaining signals CPH1, CPH2 and CPH3 for the EVEN lines is not shown in FIG. 7, but only the operation waveforms of these signals are shown in FIG. 9. It should be noted that the ODD line horizontal shift clock and the EVEN line horizontal shift clock may be replaced by each other.
FIG. 9 shows the waveforms of the ODD line horizontal shift clock and the EVEN line horizontal shift clock for the first panel. As shown in FIG. 9, a phase difference between the rising edges of signals CPH1, CPH2 and CPH3 is equal to the time period corresponding to one pixel (also referred to as “one dot”) because the first panel is a delta arrangement panel which operates based on the single-pixel sequential transfer method using the three phase shift clocks. Further, since the single-pixel sequential transfer method is employed, shift correction by 0.5 pixel is necessary in each of the ODD line and the EVEN line. Signals CPH1, CPH2 and CPH3 are delayed by one cycle of VCOCLK1 to generate signals CPH1, CPH2 and CPH3 for the EVEN lines.
As shown in FIG. 10, a phase difference between a rising edge of signal CKH2, which is an inverted signal of signal CKHO (=CKH1), and a rising edge of signal CKH1 is equal to the time period corresponding to three pixels (also referred to as “three dots”) because the second panel is a delta arrangement panel which operates based on the three-pixel simultaneous transfer method using the two-phase shift clocks. FIG. 10 shows the waveforms of the ODD line horizontal shift clock and the EVEN line horizontal shift clock for the second panel. As shown in FIG. 10, as for the horizontal shift clock for the EVEN lines, CKHE=CKH1. Shift correction of 1.5 pixel is made to the horizontal shift clock for the EVEN lines with respect to the shift clock for the ODD lines.